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ISL5740
TM
P RE L I M I NA R Y
Data Sheet
June 2000
File Number
4821.2
3V Dual 10-Bit, 20/40/60MSPS A/D Converter with Internal Voltage Reference
The ISL5740 is a monolithic, dual 10-bit analog-to-digital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. The ISL5740 features a 9-stage pipeline architecture. The fully pipelined architecture and an innovative input stage enable the ISL5740 to accept a variety of input configurations, singleended or fully differential. Only one external clock is necessary to drive both converters and an internal band-gap voltage reference is provided. This allows the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. The ISL5740 has excellent dynamic performance while consuming less than 280mW power at 60MSPS. The A/D only requires a single +3.0V power supply. Data output latches are provided which present valid data to the output bus with a latency of 5 clock cycles. The ISL5740 is offered in 20MSPS, 40MSPS and 60MSPS sampling rates.
Features
* Sampling Rate . . . . . . . . . . . . . . . . . . . . . .20/40/60MSPS * 9.1 Bits at fIN = 10MHz * Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . .280mW * Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6mW * Wide Full Power Input Bandwidth. . . . . . . . . . . . . 400MHz * SFDR at fIN = 10MHz . . . . . . . . . . . . . . . . . . . . . . . . .70dB * Excellent Channel-to-Channel Isolation . . . . . . . . . . .75dB * On-Chip Sample and Hold Amplifiers * Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V * Single Supply Voltage Operation . . . . . . . . . .+2.7V - 3.6V * TTL/CMOS(3V) Digital Inputs CMOS Digital Outputs * Offset Binary or Two's Complement Digital Data Output Format * Dual 10-Bit A/D Converters on a Monolithic Chip * Pin Compatible Upgrade to AD9288
Pinout
* Wireless Local Loop * PSK and QAM I&Q Demodulators
Ordering Information
PART NUMBER ISL5740/2IN ISL5740/3IN ISL5740/4IN ISL5740/6IN ISL5740 EVAL TEMP. RANGE (oC) PACKAGE SAMPLIN G RATE PKG. NO. (MSPS) Q48.7x7 Q48.7x7 Q48.7x7 Q48.7x7 20 30 40 60
* Medical Imaging and Instrumentation * Wireless Communications Systems * Battery Powered Instruments
-40 to 85 48 Ld LQFP -40 to 85 48 Ld LQFP -40 to 85 48 Ld LQFP -40 to 85 48 Ld LQFP 25
Pinout
AVCC I CLK DVCC GND ID9 ID7 ID6 ID8 ID4 ID3 ID5 ID2
Evaluation Platform
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
GND IIN+ IINDFS IVRIN VROUT QVRIN S1 S2 QINQIN+ GND
1 2 3 4 5 6 7 8 9 10
ID1 ID0 GND DVCC GND AVCC AVCC GND DVCC GND QD0 QD1
26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
DVCC GND
QD7 QD6
AVCC
Q CLK
QD9
QD5 QD4
QD8
QD3
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
QD2
ISL5740 Functional Block Diagram
I/QINI/QIN+ S/H CLOCK I/QCLK
STAGE 1
2-BIT FLASH
2-BIT DAC
+
-
X2 I/QD9 (MSB) I/QD8 I/QD7 I/QD6 STAGE 8 DIGITAL DELAY AND DIGITAL ERROR CORRECTION I/QD5 I/QD4 I/QD3 2-BIT FLASH 2-BIT DAC I/QD2 I/QD1 + I/QD0 (LSB)
-
X2
STAGE 9
2-BIT FLASH
I OR Q CHANNEL
VROUT I/QVRIN
REFERENCE AVCC AGND DVCC DGND
MODE DATA FORMAT
S1/S2 DFS
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ISL5740 Typical Application Schematic
ISL5740
IIN +
(2) IIN +
(LSB) ID0 (35) ID1 (36) ID2 (37) ID3 (38) ID4 (39) ID5 (40) ID6 (41) ID7 (42) ID8 (43) (MSB) ID9 (44) (LSB) QD0 (26) QD1 (25) QD2 (24) QD3 (23) QD4 (22) QD5 (21) QD6 (20) QD7 (19) QD8 (18) (MSB) QD9 (17)
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 QD0 QD1 QD2 QD3 QD4 QD5 QD6 QD7 QD8 QD9
IIN -
(3) IIN -
QIN +
(11) QIN +
QIN -
(10) QIN -
(5) IVRIN (6) QVRIN (7) VROUT
0.1F
ICLK (47) QCLK (14)
CLOCK
S1 (8) S2 (9) DFS (4) +3V 10F (13,30,31,48) AVCC DV CC (15, 28, 33, 46) 0.1F
S1 S2 DFS 3V 10F
+
+ 0.1F
(12,29,32) AGND
DGND (16, 27, 34, 45)
BNC AGND DGND
10F AND 0.1F CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE
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ISL5740 Pin Descriptions
PIN NO. 1 2 3 4 NAME AGND IIN+ IINDFS DESCRIPTION Analog Ground I-Channel Positive Analog Input I-Channel Negative Analog Input Data Format Select (Low for Offset Binary and High for Twos Complement Output Format) I-Channel Voltage Reference Input +1.25V Reference Voltage Output (Decouple with 0.1F Capacitor) Q-Channel Voltage Reference Input Mode Select Pin 1 (See Table) Mode Select Pin 2 (See Table) Q-Channel Negative Analog Input Q-Channel Positive Analog Input Analog Ground Analog Supply Q-Channel Clock Input Digital Supply Digital Ground Q-Channel, Data Bit 9 Output (MSB) Q-Channel, Data Bit 8 Output Q-Channel, Data Bit 7 Output Q-Channel, Data Bit 6 Output Q-Channel, Data Bit 5 Output Q-Channel, Data Bit 4 Output Q-Channel, Data Bit 3 Output
Pin Descriptions
PIN NO. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME QD2 QD1 QD0 DGND DVCC AGND AVCC AVCC AGND DVCC DGND ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 DGND DVCC ICLK AVCC
(Continued) DESCRIPTION Q-Channel, Data Bit 2 Output Q-Channel, Data Bit 1 Output Q-Channel, Data Bit 0 Output (LSB) Digital Ground Digital Supply Analog Ground Analog Supply Analog Supply Analog Ground Digital Supply Digital Ground I-Channel, Data Bit 0 Output (LSB) I-Channel, Data Bit 1 Output I-Channel, Data Bit 2 Output I-Channel, Data Bit 3 Output I-Channel, Data Bit 4 Output I-Channel, Data Bit 5 Output I-Channel, Data Bit 6 Output I-Channel, Data Bit 7 Output I-Channel, Data Bit 8 Output I-Channel, Data Bit 9 Output (MSB) Digital Ground Digital Supply I-Channel Clock Input Analog Supply
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
IVRIN VROUT QVRIN S1 S2 QINQIN+ AGND AVCC QCLK DVCC DGND QD9 QD8 QD7 QD6 QD5 QD4 QD3
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ISL5740
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only)
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Temperature Range ISL5740IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE Gain Matching DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate Effective Number of Bits, ENOB
AV CC = DV CC = +3.0V; I/QVRIN = 1.25V; fS = 60MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
10 fIN = 10MHz fIN = 10MHz fIN = DC fIN = DC Full Scale (Peak-to-Peak) -36 -3 -
2 0.4 12 1 1.5
1 1.0 +36 3 6
Bits LSB LSB LSB %fS %fS
No Missing Codes No Missing Codes fIN = 10MHz fIN = 10MHz
60 9.1 56.8
1 -
-
MSPS MSPS Bits dB
Signal to Noise and Distortion Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal = -----------------------------RMS Noise Total Harmonic Distortion, THD 2nd Harmonic Distortion 3rd Harmonic Distortion Spurious Free Dynamic Range, SFDR Intermodulation Distortion, IMD I/Q Channel Crosstalk I/Q Channel Offset Match I/Q Channel Full Scale Error Match Transient Response Over-Voltage Recovery
fIN = 10MHz
57
-
-
dB
fIN = 10MHz fIN = 10MHz fIN = 10MHz fIN = 10MHz f1 = 1MHz, f2 = 1.02MHz
-70 70 -
-75 10 10 1 1
-
dBc dBc dBc dBc dBc dBc LSB LSB Cycle Cycle
(Note 2) 0.2V Overdrive (Note 2)
-
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ISL5740
Electrical Specifications
PARAMETER ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (I/QIN+ - I/QIN-) Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RIN+ or RINAnalog Input Capacitance, CIN+ or CINAnalog Input Bias Current, IB+ or IBDifferential Analog Input Bias Current IBDIFF = (IB+ - IB-) Full Power Input Bandwidth, FPBW Analog Input Common Mode Voltage Range (VIN+ + VIN-) / 2 INTERNAL VOLTAGE REFERENCE Reference Output Voltage, VROUT (Loaded) Reference Output Current, IROUT Reference Temperature Coefficient REFERENCE VOLTAGE INPUT Reference Voltage Input, VRIN Total Reference Resistance, RRIN Reference Current, IRIN SAMPLING CLOCK INPUT Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Delay Match Aperture Jitter, tAJ Data Output Hold, tH Data Output Delay, tOD Data Latency, tLAT Power-Up Initialization Sample Clock Pulse Width (Low) For a Valid Sample (Note 2) Data Invalid Time (Note 2) (Note 2) 7.5 100 5 3 4.5 7 8.3 ns ps psRMS ns ns Cycles Cycles ns IOH = 100A IOL = 100A 2.45 2.98 0.001 7 0.5 V V pF CLK CLK CLK, VIH = 5V CLK, VIL = 0V CLK 2.0 -1 -1 0.8 1 1 V V A A pF With VRIN = 1.25V With VRIN = 1.25V 1.25 V M mA 1.25 1 200 V mA ppm/oC VIN+, VIN- = VREF, DC VIN+, VIN- = VREF, DC VIN+, VIN- = VREF, DC (Notes 2, 3) (Notes 2, 3) (Note 2) Differential Mode (Note 2) -10 -0.5 0.25 0.5 1.0 1 10 400 10 0.5 AVCC-0.25 V V M pF A A MHz V AV CC = DV CC = +3.0V; I/QVRIN = 1.25V; fS = 60MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified (Continued) TEST CONDITIONS MIN TYP MAX UNITS
3-6
ISL5740
Electrical Specifications
PARAMETER Sample Clock Pulse Width (High) Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVCC Digital Supply Voltage, DVCC1 and DVCC2 Supply Current Total, ICCT Analog Supply Current IACC Digital Supply Current IDCC Power Dissipation Total PT Offset Error Sensitivity, VOS Gain Error Sensitivity, FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. AVCC or DVCC = 3V 5% AVCC or DVCC = 3V 5% (Note 2) (Note 2) 2.7 2.7 3.0 3.0 0.5 0.5 3.6 3.6 93.3 68.3 25 280 V V mA mA mA mW LSB LSB (Note 2) AV CC = DV CC = +3.0V; I/QVRIN = 1.25V; fS = 60MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input, Unless Otherwise Specified (Continued) TEST CONDITIONS MIN 7.5 TYP 8.3 5 MAX UNITS ns %
3-7
ISL5740 Timing Waveforms
ANALOG INPUT
CLOCK INPUT
SN - 1
HN - 1
SN
HN
SN + 1
HN + 1 SN + 2
SN + 5 HN + 5
SN + 6 HN + 6 SN + 7
HN + 7 SN + 8
HN + 8
INPUT S/H
1ST STAGE
B1 , N - 1
B1 , N
B1 , N + 1
B1 , N + 4
B1 , N + 5
B1 , N + 6
B1 , N + 7
2ND STAGE
B2 , N - 2
B2 , N - 1
B2 , N
B2 , N + 4
B2 , N + 5
B2 , N + 6
9TH STAGE
B9 , N - 5
B9 , N - 4
B9 , N
B9 , N + 1
B9 , N + 2
B9 , N + 3
DATA OUTPUT
DN - 6
DN - 5 tLAT
DN - 1
DN
DN + 1
DN + 2
NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM , N : M-th stage digital output corresponding to N-th sampled input. 7. DN : Final data output corresponding to N-th sampled input. FIGURE 1. ISL5740 INTERNAL CIRCUIT TIMING
ANALOG INPUT tAP tAJ CLOCK INPUT 1.5V 1.5V tOD tH DATA OUTPUT 2.4V DATA N-1 0.5V DATA N
FIGURE 2. ISL5740 INPUT TO OUTPUT TIMING
3-8
ISL5740
TABLE 1. A/D CODE TABLE OFFSET BINARY OUTPUT CODE CODE CENTER DESCRIPTION +Full Scale (+fS) -1/4 LSB +fS - 11/4 LSB +3/4 LSB -1/4 LSB -fS + 13/4 LSB -Full Scale (-fS) + 3/4 LSB NOTE: 8. The voltages listed above represent the ideal center of each output code shown with VREFIN = +1.25V. DIFFERENTIAL INPUT VOLTAGE (I/QIN+ - I/QIN-) 0.499756V 0.498779V 732.422V -244.141V -0.498291V -0.499268V MSB LSB
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0 1 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0
Detailed Description
Theory of Operation
The ISL5740 is a dual 10-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 15 depicts the circuit for the front end differential-in-differentialout sample-and-hold (S/H) amplifiers. The switches are controlled by an internal sampling clock which is a nonoverlapping two phase signal, 1 and 2 , derived from the master sampling clock. During the sampling phase, 1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of 1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-andhold function but will also convert a single-ended input to a fully-differential output for the converter core. During the sampling phase, the I/QIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 400MHz for the converter.
I/QIN+
1 1 2
I/QINCS
CH
1
VOUT+ VOUT-
-+
+CS
1
1
CH
1
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the Functional Block Diagram and the timing diagram in Figure 1, eight identical pipeline subconverter stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H circuit with the ninth stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The output of each of the eight identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the eight identical two-bit subconverter stages with the corresponding output of the ninth stage flash converter before applying the eighteen bit result to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clock after the
3-9
ISL5740
analog sample is taken (see the timing diagram in Figure 1). This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital output data is provided in offset binary format (see Table 1, A/D Code Table). significantly with the value of the analog input common mode voltage. For the AC coupled differential input (Figure 16) and with VRIN connected to VROUT, full scale is achieved when the VIN and -VIN input signals are 0.5VP-P, with -VIN being 180 degrees out of phase with VIN . The converter will be at positive full scale when the I/QIN+ input is at I/QVRIN + 0.25V and the I/QIN- input is at I/QVRIN - 0.25V (I/QIN+ - I/QIN- = +0.5V). Conversely, the converter will be at negative full scale when the I/QIN+ input is equal to I/QVRIN - 0.25V and I/QIN- is at I/QVRIN + 0.25V (I/QIN+ - I/QIN- = -0.5V). The analog input can be DC coupled (Figure 17) as long as the inputs are within the analog input common mode voltage range (0.25V VDC 2.75V). The resistors, R, in Figure 17 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from I/QIN+ to I/QIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal.
VIN VDC R C I/QIN+ ISL5740 I/QVRIN -VIN VDC R I/QIN-
Internal Reference Voltage Output, VROUT
The ISL5740 is equipped with an internal 1.25V bandgap reference voltage generator, therefore, no external reference voltage is required. VROUT should be connected to VRIN when using the internal reference voltage. An external, usersupplied, 0.1F capacitor may be connected from the VROUT output pin to filter any stray board noise.
Reference Voltage Inputs, I/Q VREFIN
The ISL5740 is designed to accept a 1.25V reference voltage source at the VRIN input pins for the I and Q channels. Typical operation of the converter requires VRIN to be set at 1.25V. The ISL5740 is tested with VRIN connected to VROUT yielding a fully differential analog input voltage range of 0.5V. The user does have the option of supplying an external 1.25V reference voltage. As a result of the high input impedance presented at the VRIN input pin, M typically, the external reference voltage being used is only required to source small amount of reference input current. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VRIN .
Analog Input, Differential Connection
The analog input of the ISL5740 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 16 and Figure 17) will deliver the best performance from the converter.
FIGURE 5. DC COUPLED DIFFERENTIAL INPUT
Analog Input, Single-Ended Connection
VIN R I/QIN+ ISL5740 I/QVRIN R -VIN I/QINVIN R VDC ISL5740 I/QINI/QIN+
The configuration shown in Figure 18 may be used with a single ended AC coupled input.
FIGURE 4. AC COUPLED DIFFERENTIAL INPUT
Since the ISL5740 is powered by a single +3V analog supply, the analog input is limited to be between ground and +3V. For the differential input connection this implies the analog input common mode voltage can range from 0.25V to 2.75V. The performance of the ADC does not change
FIGURE 6. AC COUPLED SINGLE ENDED INPUT
Again, with VRIN connected to VROUT, if VIN is a 1VP-P sinewave, then I/QIN+ is a 1.0VP-P sinewave riding on a positive voltage equal to VDC . The converter will be at positive full scale when I/QIN+ is at VDC + 0.5V (I/QIN+ -
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ISL5740
I/QIN- = +0.5V) and will be at negative full scale when I/QIN+ is equal to VDC - 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient headroom must be provided such that the input voltage never goes above +3V or below AGND. In this case, VDC could range between 0.5V and 2.5V without a significant change in ADC performance. The simplest way to produce VDC is to use the I/QVRIN bias source, I/QVDC , output of the ISL5740. The single ended analog input can be DC coupled (Figure 19) as long as the input is within the analog input common mode voltage range.
VIN VDC R C ISL5740 I/QIN+
OPERATIONAL MODES S1 0 0 1 1 S2 0 1 0 1 MODE Standby I and Q Channels. I channel operates normally with Q Channel in standby mode. I and Q Channels operating with I/Q output data in phase. I and Q Channels operating with Q data 180 degrees out of phase.
Sampling Clock Requirements
The ISL5740 sampling clock input provides a standard highspeed interface to external TTL/CMOS logic families. In order to ensure rated performance of the ISL5740, the duty cycle of the clock should be held at 50% 5%. It must also have low jitter and operate at standard TTL/CMOS levels. Performance of the ISL5740 will only be guaranteed at conversion rates above 1MSPS (Typ). This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1MSPS must be performed before valid data is available.
VDC
I/QIN-
FIGURE 7. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 19 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from I/QIN+ to I/QIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the ISL5740.
Supply and Ground Considerations
The ISL5740 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the ISL5740 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply can be isolated by a ferrite bead from the digital supply. Refer to the application note "Using Intersil High Speed A/D Converters" (AN9214) for additional considerations when using high speed converters.
Operational Mode
The ISL5740 contains several operational modes including a normal two channel operation, placing one or both channels in standby and delaying the Q channel data 1/2 clock cycle. The operational mode is selected via the S1 and S2 pins and is asynchronous to either clock. When either channel is placed in standby, the output data is stalled and not high impedance. When recovering from standby, valid data is available after 20 clock cycles. The delay mode can be used to set the Q channel 180 degrees out phase of the I channel if the same clock is driving both channels. If separate, inverted clocks are used for the I and Q channels, this feature can be used to align the data.
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ISL5740
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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